1. Field of the Invention.
This invention relates to integrated circuit charge pumps and, more particularly, to charge pumps for more effectively providing programming voltages to anti-fuse read only memory (ROM) devices.
2. Prior Art
An anti-fuse ROM device is composed of an array of columns and rows, or words, of memory cells, where each memory cell includes an anti-fuse element in one of two logic states, that is, in either a unprogrammed, high-resistance state or in a programmed, low-resistance state. A column, or bit, select line has a number of memory cells containing anti-fuse elements, or links, connected thereto. An unprogrammed anti-fuse link has a resistance on the order of 1 gigohm, and a programmed anti-fuse link has a resistance on the order of 200 ohms.
For programming a typical anti-fuse link, one terminal of the anti-fuse link is connected to a high voltage programming current source using the column select line. The other terminal of the anti-fuse link is connected to a drain terminal of a word, or row, select transistor. The source terminal of the word select transistor is connected to ground. The gate terminal of the word select transistor is connected to a word line. To program an anti-fuse link, a word-select signal is applied to the word line. This turns on the word select transistor and connects the high voltage programming current source to the anti-fuse link. Other anti-fuse links of a memory array are similarly programmed by similar selection of a column and a row.
One prior art technique for providing programming voltages to a row-and-column array of anti-fuse read only memory (ROM) device uses a charge pump to boost the gate voltage provided to the gate terminals of a column of cell selection transistors. Each one of the cell-selection transistors connects one particular anti-fuse element of a column of anti-fuse elements to a high-voltage programming current source. A word-selection transistor grounds the other ends of a row of anti-fuse elements. A particular anti-fuse element is selected for programming by selecting an appropriate column for one terminal of a selected fuse element applying a boosted gate voltage thereto. The boosted gate voltage causes a high-voltage programming current source to be connected to a selected anti-fuse element.
During normal operation, an anti-fuse ROM is operated with a VCC voltage of 5 volts. During a programming operation, it is desirable the VCC voltage for an anti-fuse ROM be boosted to a higher voltage, such as 6.5 volts, in order to improve the chances of programming marginal cells and to obtain better yields. However, a problem arises when operating an anti-fuse ROM at 6.5 volts during a programming operation. That problem is that the various standard circuits used to provide the logic signals and the addressing signals to the memory do not function at a VCC of 6.5 v. As a result a VCC voltage of 5.5 volts must be used during programming operations.
It has been found that the column selection circuitry using a higher VCC voltage of 6.5 volts works with, for example, devices produced with a memory-device fabrication process with a 0.8 micron geometry. But, using a lower VCC of 5.5 volts does not work with a memory process having a smaller geometry such as, for example, a 0.6 micron process. In the smaller geometry process, the voltage for the high voltage programming current source is lower and a 5.5 volt VCC must be used. However, for a 0.6 micron process, the conventional charge pump circuit used in the larger geometry processes of does not operate.
A need has arisen for a technique for providing programming voltages to anti-fuse ROM devices with smaller geometry memory cells within the VCC voltage constraints required for logic and addressing functions.
FIG I shows a conventional circuit 100 used for addressing and programming an anti-fuse link in memory cells (typically shown as 102), where the memory cells are arranged in columns and rows. The circuit 100 was used for previous generations of anti-fuse memory devices. As integrated-circuit elements grow smaller due to improvements in processing technology, programming smaller geometry memory cells within more limited voltage constraints requires improvements to the circuits in order to handle constraints imposed by smaller geometries.
A typical memory cell 102 includes an anti-fuse link 104 having a first terminal and a second terminal. An unprogrammed anti-fuse link has a resistance on the order of 1 gigohm, and a programmed anti-fuse link has a resistance on the order of 200 ohms. There is a column selection transistor 106 having a drain terminal connected to a line 108 which is connected to a high-voltage (13 volts, for example) programming current source. The column-selection transistor 106 has a source terminal which is connected to one terminal of a number of anti-fuse links including 104. A gate terminal is connected to a line 110 on which is provided a boosted column-select signal.
Another problem with prior programming techniques for providing programming voltages for anti-fuse ROM device is junction breakdown. A charge pump circuit provides a voltage which ramps up until the junction breakdown voltage is reached. This limits how high the voltage output of the charge pump can go. In prior art circuits, the voltage provided at the top of an anti-fuse link is body effect plus two threshold voltage drops down from the charge-pump output voltage, or approximately 4 volts down, from the junction breakdown voltage of the charge-pump transistor. The memory cell 102 also includes a word-selection transistor 112 which has a drain terminal connected to the second terminal of the anti-fuse link 104. The word selection transistor 112 has a source terminal connected to a ground reference voltage. A gate terminal of the word selection transistor 112 is connected to a word selection line, or word line 114.
A column is selected with a high-voltage blocking transistor 116 which has a drain terminal connected to a SHIFT REGISTER OUTPUT terminal 118 at which is provided a column-select signal from a column-select shift register (not shown). The column-select signal activates the high-voltage blocking transistor 116 by providing a VCC signal on the drain of high-voltage blocking transistor 116, which has a gate terminal connected to a VCC voltage and which a source terminal connected to line 110. Line 110 is provided with a boosted column-select signal using a charge pump circuit 120, which includes transistors 122, 124, 126. Transistor 122 has a drain terminal connected to a line 128 on which is provided HIGH VOLTAGE SETUP voltage between 10 and 13 volts. A gate terminal of transistor 122 is connected to line 110. A source terminal of transistor 122 is connected to a terminal 130. Transistor 124 has a drain terminal and a gate terminal connected to terminal 130. The source terminal of transistor 124 is connected to line 110.
Transistor 126 is connected as a capacitor with its gate terminal connected to terminal 130 and with its source and drain terminals connected to an OSC line 132, on which is provided an oscillator signal alternating between zero volts and VCC.
The column-select shift register selects the particular column shown in FIG. 1 of the memory array by providing a VCC-level signal at the SHIFT REGISTER OUTPUT terminal 118. The shift register selects a particular column of the prior art larger geometry circuit shown in FIG. 1 by delivering a 6.5 volt signal to the top of transistor 116. This 6.5 volt signal passes through transistor 116 to put approximately 5 volts on line 110. This approximately 5 volt signal on line 110 turns on transistor 122 which, in turn, passes on approximately 3.5 volts to the gate terminal of transistor 126 which turns on transistor 126. Transistor 126 functions as a capacitor.
Charge pump circuit 120 depicts a typical charge pump configuration. During the positive swing of the oscillator signal on OSC line 132, line 132 delivers charge through transistor 126 and through transistor 124 to line 110. That charge is trapped on line 110 to thereby increase, or boost, the voltage on line 110. This boost in the voltage on line 110 also causes transistor 122 to supply additional charge to node 130 at the same time that the capacitor-connected transistor 126 tries to take back charge during the negative swing on OSC line 132. The next positive swing of the oscillator voltage rides on top of the voltage on node 130 which results in even more voltage on line 110. This cycle is repeated and allows the voltage on 110 to increase past the point where transistor 116 is cut off.
It has also been found that the prior art configuration of FIG. 1 has a problem when it is used with newer, smaller integrated-circuit device geometries. The problem is that the various library cells used to provide logic signals and addressing to the memory cell do not work at a VCC of 6.5 v. This requires a VCC of 5.5 volts to be used during programming. Memory cells for the newer, smaller device geometries have lower breakdown voltages. While a lower VCC was found to work for prior larger device geometries, it does not work for the newer, smaller device geometries, where a 5.5 volt VCC is used along with a lower voltage for a high-voltage programming charge source. Under the conditions required by the smaller device geometries, a charge pump circuit does not function. The circuit shown in FIG. 1 is unable to program anti-fuse devices using the newer, smaller device geometries. In the prior art, the highest breakdown voltage occurs at node 130. If the junction breakdown voltage is 17 volts, this voltage limits every other voltage throughout the circuit, such as 15 volts at line 110 and 13 volts at the anti-fuse link 104.
What is needed is a charge pump circuit for providing high-voltage programming and control voltages for anti-fuse read only memory (ROM) devices and for other applications where the charge-pump circuit is not limited by the breakdown voltages of its transistor elements.